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| SN54/74LS74A DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the HIGH or the LOW level, the D input signal has no effect. DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP LOW POWER SCHOTTKY LOGIC DIAGRAM (Each Flip-Flop) 14 1 J SUFFIX CERAMIC CASE 632-08 SET (SD) 4 (10) Q 5 (9) CLEAR (CD) 1 (13) CLOCK 3 (11) D 2 (12) 14 N SUFFIX PLASTIC CASE 646-06 1 Q 6 (8) 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION MODE SELECT -- TRUTH TABLE INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Load "1" (Set) Load "0" (Reset) L H L H H SD H L L H H D X X X h l Q H L H H L Q L H H L H OUTPUTS SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 2 3 D SD Q CP CD Q 1 VCC = PIN 14 GND = PIN 7 6 5 12 11 10 D SD Q CP CD Q 13 8 9 * Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. If the levels at the set and clear are near VIL maximum then we cannot guarantee to meet the minimum level for VOH. H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Don't Care i, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time i, h (q) = prior to the HIGH to LOW clock transition. FAST AND LS TTL DATA 5-1 SN54/74LS74A GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54 74 54, 74 VOL Output LOW Voltage 74 Input High Current Data, Clock Set, Clear Data, Clock Set, Clear IIL IOS ICC Input LOW Current Data, Clock Set, Clear Output Short Circuit Current (Note 1) Power Supply Current - 20 0.35 0.5 20 40 0.1 0.2 - 0.4 - 0.8 -100 8.0 V A 2.5 2.7 54 74 - 0.65 3.5 3.5 0.25 0.4 Min 2.0 0.7 0.8 - 1.5 Typ Max Unit Ui V V V V V V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH , , or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V IIH mA VCC = MAX, VIN = 7.0 V mA mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl fMAX tPLH tPHL Parameter P Maximum Clock Frequency Clock, Clear, Clock Clear Set to Output Min 25 Typ 33 13 25 25 40 Max Unit Ui MHz ns ns Test C di i T Conditions Figure 1 Figure 1 VCC = 5.0 V 50 CL = 15 pF AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol S bl tW (H) tW (L) ts th Clock Clear, Set Data Setup Time -- HIGH p Data Setup Time -- LOW Hold Time Parameter P Min 25 25 20 20 5.0 Typ Max Unit Ui ns ns ns Figure 1 ns ns Figure 1 Test C di i T Conditions Figure 1 Figure 2 VCC = 5.0 V 50 FAST AND LS TTL DATA 5-2 SN54/74LS74A AC WAVEFORMS D* 1.3 V th(L) ts(L) 1.3 V tW(H) 1.3 V th(H) ts(H) tW(L) 1.3 V 1 fMAX CP tPHL Q 1.3 V tPHL 1.3 V tPLH 1.3 V tPLH 1.3 V Q *The shaded areas indicate when the input is permitted to change for predictable output performance. Figure 1. Clock to Output Delays, Data Set-Up and Hold Times, Clock Pulse Width tW SET 1.3 V 1.3 V tW CLEAR tPLH 1.3 V tPHL Q 1.3 V tPHL 1.3 V tPLH 1.3 V Q 1.3 V 1.3 V Figure 2. Set and Clear to Output Delays, Set and Clear Pulse Widths FAST AND LS TTL DATA 5-3 |
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